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14-bit, 20 msps/40 msps/65 msps dual a/d converter ad9248 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2010 analog devices, inc. all rights reserved. features integrated dual 14-bit adc single 3 v supply operation (2.7 v to 3.6 v) snr = 71.6 db (to nyquist, ad9248-65) sfdr = 80.5 dbc (to nyquist, ad9248-65) low power: 300 mw/channel at 65 msps differential input with 500 mhz, 3 db bandwidth exceptional crosstalk immunity > 85 db flexible analog input: 1 v p-p to 2 v p-p range offset binary or twos complement data format clock duty cycle stabilizer output datamux option applications ultrasound equipment direct conversion or if sampling receivers wb-cdma, cdma2000, wimax battery-powered instruments hand-held scopemeters low cost digital oscilloscopes general description the ad9248 is a dual, 3 v, 14-bit, 20 msps/40 msps/65 msps analog-to-digital converter (adc). it features dual high performance sample-and hold amplifiers (shas) and an integrated voltage reference. the ad9248 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy and to guarantee no missing codes over the full operating temperature range at up to 65 msps data rates. the wide bandwidth, differential sha allows for a variety of user-selectable input ranges and offsets, including single-ended applications. it is suitable for various applications, including multiplexed systems that switch full- scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the nyquist rate. dual single-ended clock inputs are used to control all internal conversion cycles. a duty cycle stabilizer is available and can compensate for wide variations in the clock duty cycle, allowing the converter to maintain excellent performance. the digital output data is presented in either straight binary or twos complement format. out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. functional block diagram vin+_a vin?_a reft_a refb_a vref sense agnd reft_b refb_b vin+_b vin?_b otr_a d13_a to d0_a oeb_a mux_select clk_a clk_b dcs shared_ref pwdn_a pwdn_b dfs otr_b d13_b to d0_b oeb_b avdd agnd drvdd drgnd 14 ad9248 14 0.5v output mux/ buffers 14 14 output mux/ buffers clock duty cycle stabilizer mode control adc sha sha 04446-001 adc figure 1. fabricated on an advanced cmos process, the ad9248 is available in a pb-free, space saving, 64-lead lqfp or lfcsp and is specified over the industrial temperature range (?40c to +85c). product highlights 1. pin-compatible with the ad9238, 12-bit 20 msps/ 40 msps/65 msps adc. 2. speed grade options of 20 msps, 40 msps, and 65 msps allow flexibility between power, cost, and performance to suit an application. 3. low power consumption: ad9248-65: 65 msps = 600 mw, ad9248-40: 40 msps = 330 mw, and ad9248-20: 20 msps = 180 mw. 4. typical channel isolation of 85 db @ f in = 10 mhz. 5. the clock duty cycle stabilizer (ad9248-20/ad9248-40/ ad9248-65) maintains performance over a wide range of clock duty cycles. 6. multiplexed data output option enables single-port operation from either data port a or data port b.
ad9248 rev. b | page 2 of 48 table of contents specifications ..................................................................................... 3 ? dc specifications ......................................................................... 3 ? ac specifications .......................................................................... 5 ? digital specifications ................................................................... 6 ? switching specifications .............................................................. 7 ? absolute maximum ratings ............................................................ 8 ? explanation of test levels ........................................................... 8 ? esd caution .................................................................................. 8 ? pin configurations and function descriptions ........................... 9 ? te r m i no l o g y .................................................................................... 11 ? typical performance characteristics ........................................... 12 ? equivalent circuits ......................................................................... 16 ? theory of operation ...................................................................... 17 ? analog input ............................................................................... 17 ? clock input and considerations .............................................. 18 ? power dissipation and standby mode ..................................... 19 ? digital outputs ........................................................................... 19 ? timing .......................................................................................... 19 ? data format ................................................................................ 20 ? voltage reference ....................................................................... 20 ? ad9248 lqfp evaluation board ................................................. 22 ? clock circuitry ........................................................................... 22 ? analog inputs ............................................................................. 22 ? reference circuitry .................................................................... 22 ? digital control logic ................................................................. 22 ? outputs ........................................................................................ 22 ? lqfp evaluation board bill of materials (bom) .................. 24 ? lqfp evaluation board schematics ........................................ 25 ? lqfp pcb layers ....................................................................... 29 ? dual adc lfcsp pcb .................................................................. 35 ? power connector ........................................................................ 35 ? analog inputs ............................................................................. 35 ? optional operational amplifier .............................................. 35 ? clock ............................................................................................ 35 ? volt age reference ....................................................................... 35 ? data outputs ............................................................................... 35 ? lfcsp evaluation board bill of materials (bom) ................ 36 ? lfcsp pcb schematics ............................................................. 37 ? lfcsp pcb layers ..................................................................... 40 ? thermal considerations ............................................................ 45 ? outline dimensions ....................................................................... 46 ? ordering guide .......................................................................... 47 ? revision history 11/10rev. a to rev. b changes to absolute maximum ratings section ......................... 8 changes to figure 3 .......................................................................... 9 add figure 4; renumbered sequentially ....................................... 9 changes to theory of operation section and analog input section .............................................................................................. 17 deleted note 1 from dual adc lfcsp pcb section ............... 35 updated outline dimensions ....................................................... 46 3/05rev. 0 to rev. a added lfcsp ...................................................................... universal changes to features .......................................................................... 1 changes to applications .................................................................. 1 changes to general description .................................................... 1 changes to product highlights ....................................................... 1 changes to table 6 .......................................................................... 10 changes to terminology ............................................................... 11 changes to figure 22 ...................................................................... 15 changes to clock input and considerations section ................ 18 changes to timing section ........................................................... 19 changes to figure 33 ...................................................................... 19 changes to data format section .................................................. 20 changes to table 10 ....................................................................... 24 changes to figure 39 ...................................................................... 25 changes to table 13 ....................................................................... 36 updated outline dimensions ....................................................... 46 changes to ordering guide .......................................................... 47 1/05revision 0: initial version
ad9248 rev. b | page 3 of 48 specifications dc specifications avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clk_a = clk_b; a in = ?0.5 dbfs differential input, 1.0 v internal reference, t min to t max , dcs enabled, unless otherwise noted. table 1. test ad9248bst/bcp-20 ad9248bst/bcp-40 ad9248bst/bcp-65 parameter temp level min typ max min typ max min typ max unit resolution full vi 14 14 14 bits accuracy no missing codes guaranteed full vi 14 14 14 bits offset error 25c i 0.2 1.3 0.2 1.3 0.2 1.3 % fsr gain error 1 full iv 0.25 2.2 0.3 2.4 0.5 2.5 % fsr differential nonlinearity (dnl) 2 full v 0.65 0.65 0.7 lsb 25c iv 0.6 1.0 0.6 1.0 0.65 1.0 lsb integral nonlinearity (inl) 2 full v 2.7 2.7 2.8 lsb 25c iv 2.3 4.5 2.3 4.5 2.4 4.5 lsb temperature drift offset error full v 2 2 3 ppm/c gain error 1 full v 12 12 12 ppm/c internal voltage reference output voltage error (1 v mode) full vi 5 35 5 35 5 35 mv load regulation @ 1.0 ma full v 0.8 0.8 0.8 mv output voltage error (0.5 v mode) full v 2.5 2.5 2.5 mv load regulation @ 0.5 ma full v 0.1 0.1 0.1 mv input referred noise input span = 1 v 25c v 2.1 2.1 2.1 lsb rms input span = 2.0 v 25c v 1.05 1.05 1.05 lsb rms analog input input span = 1.0 v full iv 1 1 1 v p-p input span = 2.0 v full iv 2 2 2 v p-p input capacitance 3 full v 7 7 7 pf reference input resistance full v 7 7 7 k power supplies supply voltages avdd full iv 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 v drvdd full iv 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 v supply current iavdd 2 full v 60 110 200 ma idrvdd 2 full v 5 11 16 ma psrr full v 0.01 0.01 0.01 % fsr power consumption dc input 4 full v 180 330 600 mw sine wave input 2 full vi 190 217 360 400 640 700 mw standby power 5 full v 2.0 2.0 2.0 mw
ad9248 rev. b | page 4 of 48 test ad9248bst/bcp-20 ad9248bst/bcp-40 ad9248bst/bcp-65 parameter temp level min typ max min typ max min typ max unit matching characteristics offset error (nonshared reference mode) 25c i 0.19 1.56 0.19 1.56 0.25 1.74 % fsr offset error (shared reference mode) 25c i 0.19 1.56 0.19 1.56 0.25 1.74 % fsr gain error (nonshared reference mode) 25c i 0.07 1.43 0.07 1.43 0.07 1.47 % fsr gain error (shared reference mode) 25c i 0.01 0.06 0.01 0.06 0.01 0.10 % fsr 1 gain error and gain temperature coefficient are based on the adc only (with a fixed 1.0 v external reference). 2 measured at maximum clock rate with a low frequency sine wave input and approximately 5 pf lo ading on each output bit. 3 input capacitance refers to the effective capacitance between one differential input pin and avss. refer to figure for the equivalent analog input structure. 29 4 measured with dc input at maximum clock rate. 5 standby power is measured with the clk_a and clk_ b pins inactive (that is, set to avdd or agnd).
ad9248 rev. b | page 5 of 48 ac specifications avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clk_a = clk_b; a in = ?0.5 dbfs differential input, 1.0 v external reference, t min to t max , dcs enabled, unless otherwise noted. table 2. test ad9248bst/bcp-20 ad9248bst/bcp-40 ad9248bst/bcp-65 parameter temp level min typ max min typ max min typ max unit signal-to-noise ratio (snr) f input = 2.4 mhz full v 73.4 73.1 72.8 db 25c iv 73.1 73.7 72.8 73.4 72.3 73.1 db f input = 9.7 mhz full v 72.9 db 25c iv 72.4 73.1 db f input = 19.6 mhz full v 72.7 db 25c iv 72.3 72.9 db f input = 35 mhz full v 71.5 db 25c iv 71.2 71.6 db f input = 100 mhz 25c v 70 69.5 69.0 db signal-to-noise and distortion ratio (sinad) f input = 2.4 mhz full v 73.0 72.8 72.5 db 25c iv 72.2 73.2 72.0 73.0 71.7 72.7 db f input = 9.7 mhz full v 72.0 db 25c iv 70.9 72.2 db f input = 19.6 mhz full v 72.1 db 25c iv 71.0 72.3 db f input = 35 mhz full v 70.9 db 25c iv 70.0 71.0 db f input = 100 mhz 25c v 69.5 69.0 68.5 db effective number of bits (enob) f input = 2.4 mhz full v 11.8 11.8 11.8 bits 25c iv 11.7 11.8 11.7 11.8 11.6 11.8 bits f input = 9.7 mhz full v 11.7 bits 25c iv 11.5 11.7 bits f input = 19.6 mhz full v 11.7 bits 25c iv 11.5 11.7 bits f input = 35 mhz full v 11.5 bits 25c iv 11.3 11.5 bits f input = 100 mhz 25c v 11.3 11.2 11.2 bits worst harmonic (second or third) f input = 2.4 mhz full v 86.0 85.0 84.0 dbc 25c iv 77.5 87.5 77.5 86.0 77.5 86.0 dbc f input = 9.7 mhz full v 83.0 dbc 25c i 76.1 84.0 dbc f input = 19.6 mhz full v 83.0 dbc 25c i 76.0 84.0 dbc f input = 35 mhz full v 80.0 dbc 25c i 73.0 80.5 dbc
ad9248 rev. b | page 6 of 48 test ad9248bst/bcp-20 ad9248bst/bcp-40 ad9248bst/bcp-65 parameter temp level min typ max min typ max min typ max unit worst other spur (nonsecond or third) f input = 2.4 mhz full v 88.0 88.0 85.5 dbc 25c i 83.3 89.0 83.5 89.0 81.0 86.0 dbc f input = 9.7 mhz full v 87.0 dbc 25c i 83.1 88.0 dbc f input = 19.6 mhz full v 88.0 dbc 25c i 82.6 88.5 dbc f input = 35 mhz full v 85.5 dbc 25c i 79.8 86.0 dbc f input = 100 mhz 25c v 79.0 81.0 75.0 dbc spurious-free dynamic range (sfdr) f input = 2.4 mhz full v 86.0 85.0 84.0 dbc 25c iv 77.5 87.5 77.5 86.0 77.5 86.0 dbc f input = 9.7 mhz full v 83.0 dbc 25c i 76.1 84.0 dbc f input = 19.6 mhz full v 83.0 dbc 25c i 76.0 84.0 dbc f input = 35 mhz full v 80.0 dbc 25c i 73.0 80.5 dbc crosstalk full v ?85.0 ?85.0 ?85.0 db digital specifications avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clk_a = clk_b; a in = ?0.5 dbfs differential input, 1.0 v internal reference, t min to t max , dcs enabled, unless otherwise noted. table 3. test ad9248bst/bcp-20 ad9248bst-40 ad9248bst-65 parameter temp level min typ max min typ max min typ max unit logic inputs high level input voltage full iv 2.0 2.0 2.0 v low level input voltage full iv 0.8 0.8 0.8 v high level input current full iv ?10 +10 ?10 +10 ?10 +10 a low level input current full iv ? 10 +10 ?10 +10 ?10 +10 a input capacitance full iv 2 2 2 pf logic outputs 1 high level output voltage full iv drvdd ? 0.05 drvdd ? 0.05 drvdd ? 0.05 v low level output voltage full iv 0.05 0.05 0.05 v 1 output voltage levels measured with capacitive load only on each output.
ad9248 rev. b | page 7 of 48 switching specifications avdd = 3 v, drvdd = 2.5 v, maximum sample rate, clk_a = clk_b; a in = ?0.5 dbfs differential input, 1.0 v internal reference, t min to t max , dcs enabled, unless otherwise noted. table 4. test ad9248bst/bcp-20 ad9248bst/bcp-40 ad9248bst/bcp-65 parameter temp level min typ max min typ max min typ max unit switching performance maximum conversion rate full vi 20 40 65 msps minimum conversion rate full v 1 1 1 msps clk period full v 50.0 25.0 15.4 ns clk pulse-width high 1 full v 15.0 8.8 6.2 ns clk pulse-width low 1 full v 15.0 8.8 6.2 ns data output parameter output delay 2 (t pd ) full vi 2 3.5 6 2 3.5 6 2 3.5 6 ns pipeline delay (latency) full v 7 7 7 cycles aperture delay (t a ) full v 1.0 1.0 1.0 ns aperture uncertainty (t j ) full v 0.5 0.5 0.5 ps rms wake-up time 3 full v 2.5 2.5 2.5 ms out-of-range recovery time full v 2 2 2 cycles 1 the ad9248-65 model has a duty cycl e stabilizer circuit that , when enabled, corrects for a wide range of duty cycles (see figu re 24). 2 output delay is measured from clock 50% transition to data 50% transition, with a 5 pf load on each output. 3 wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 f and 10 f capacitors on reft and refb. n?1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 a nalog input clock data out n?9 n?8 n?7 n?6 n?5 n?4 n?3 n?2 n?1 n min 2.0ns, max 6.0ns t pd = 04446-002 figure 2. timing diagram
ad9248 rev. b | page 8 of 48 absolute maximum ratings absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period may affect device reliability. table 5. parameter rating electrical avdd to agnd ?0.3 v to +3.9 v drvdd to drgnd ?0.3 v to +3.9 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?3.9 v to +3.9 v digital outputs to drgnd ?0.3 v to drvdd + 0.3 v oeb, dfs, clk, dcs, mux_select, shared_ref to agnd ?0.3 v to avdd + 0.3 v vina, vinb to agnd ?0.3 v to avdd + 0.3 v vref to agnd ?0.3 v to avdd + 0.3 v sense to agnd ?0.3 v to avdd + 0.3 v refb, reft to agnd ?0.3 v to avdd + 0.3 v pdwn to agnd ?0.3 v to avdd + 0.3 v environmental 1 operating temperature ?40c to +85c junction temperature 150c lead temperature (10 sec) 300c storage temperature ?65c to +150c 1 typical thermal impedances: 64-lead lqfp, ja = 54c/w; 64-lead lfcsp, ja = 26.4c/w with heat slug soldered to ground plane. these measurements were taken on a 4-layer board in stil l air, in accordance with eia/jesd51-7. explanation of test levels i 100% production tested. ii 100% production tested at 25c and sample tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at 25c; guaranteed by design and characterization testing for in dustrial temperature range; 100% production tested at temperature extremes for military devices. esd caution
ad9248 rev. b | page 9 of 48 pin configurations and function descriptions 64 avdd 63 clk_a 62 shared_ref 61 mux_select 60 pdwn_a 59 oeb_a 58 otr_a 57 d13_a (msb) 56 d12_a 55 d11_a 54 d10_a 53 drgnd 52 drvdd 51 d9_a 50 d8_a 49 d7_a 47 d5_a 46 d4_a 45 d3_a 42 d0_a (lsb) 43 d1_a 44 d2_a 48 d6_a 41 drvdd 40 drgnd 39 otr_b 37 d12_b 36 d11_b 35 d10_b 34 d9_b 33 d8_b 38 d13_b (msb) 2 vin+_a 3 vin?_a 4 agnd 7 refb_a 6 reft_a 5 avdd 1 agnd 8 vref 9 sense 10 refb_b 12 avdd 13 agnd 14 vin?_b 15 vin+_b 16 agnd 11 reft_b pin 1 17 avdd 18 clk_b 19 dcs 20 dfs 21 pdwn_b 22 oeb_b 23 d0_b (lsb) 24 d1_b 25 d2_b 26 d3_b 27 d4_b 28 drgnd 29 drvdd 30 d5_b 31 d6_b 32 d7_b ad9248 top view (not to scale) 64-lead lqfp 04446-003 figure 3. 64-lead lqfp pin configuration 64-lead lfcsp top view (not to scale) d6_a d5_a d4_a d3_a d2_a d1_a d0_a (lsb) drgnd otr_b d13_b (msb) d12_b d11_b d10_b d9_b d8_b ad9248 agnd avdd reft_a refb_ a vref sense refb_b agnd vin?_b vin+_b vin+_a vin?_a avdd reft_b clk_a shared_ref mux_select oeb_a d13_a (msb) d12_a d11_a d10_a drgnd d9_a d8_a d7_a clk_b dcs dfs pdwn_b oeb_b d1_b d2_b d3_b d4_b drgnd d5_b d6_b d7_b d0_b (lsb) agnd agnd avdd drvdd drvdd avdd pdwn_a otr_a drvdd pin 1 indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 notes 1. there is an exposed pad that must connect to agnd. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 04446-103 figure 4. 64-lead lfcsp pin configuration
ad9248 rev. b | page 10 of 48 table 6. 64-lead lqfp and 64-lead lfcsp pin function descriptions pin no. mnemonic description 1, 4, 13, 16 agnd analog ground. 2 vin+_a analog input pin (+) for channel a. 3 vin?_a analog input pin (?) for channel a. 5, 12, 17, 64 avdd analog power supply. 6 reft_a differential reference (+) for channel a. 7 refb_a differential reference (?) for channel a. 8 vref voltage reference input/output. 9 sense reference mode selection. 10 refb_b differential reference (?) for channel b. 11 reft_b differential reference (+) for channel b. 14 vin?_b analog input pin (?) for channel b. 15 vin+_b analog input pin (+) for channel b. 18 clk_b clock input pin for channel b. 19 dcs enable duty cycle stabilizer (dcs) mode. 20 dfs data output format select pin (low for offset binary, high fo r twos complement). 21 pdwn_b power-down function selection for channel b. logic 0 enables channel b. logic 1 powers down channel b (outputs static, not high-z). 22 oeb_b output enable pin for channel b. logic 0 enables data bus b. lo gic 1 sets outputs to high-z. 23 to 27, 30 to 38 d0_b (lsb) to d13_b (msb) channel b data output bits. 28, 40, 53 drgnd digital output ground. 29, 41, 52 drvdd digital output driver supply. must be decouple d to drgnd with a minimum 0.1 f capacitor. recommended decoupling is 0.1 f capacitor in parallel with 10 f capacitor. 39 otr_b out-of-range indicator for channel b. 42 to 51, 54 to 57 d0_a (lsb) to d13_a (msb) channel a data output bits. 58 otr_a out-of-range indicator for channel a. 59 oeb_a output enable pin for channel a. logic 0 enables data bus a. lo gic 1 sets outputs to high-z. 60 pdwn_a power-down function selection for channel a. logic 0 enables channel a. logic 1 powers do wn channel a (outputs static, not high-z). 61 mux_select data multiplexed mode. (see data format section for how to enable; high setting disables output data multiplexed mode.) 62 shared_ref shared reference control pin (low for independent reference mode, high fo r shared reference mode). 63 clk_a clock input pin for channel a. ep for the 64-lead lfcsp only, there is an exposed pad that must connect to agnd.
ad9248 rev. b | page 11 of 48 terminology aperture delay sha performance measured from the rising edge of the clock input to when the input signal is held for conversion. aperture jitter the variation in aperture delay for successive samples, which is manifested as noise on the input to the adc. integral nonlinearity (inl) deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges. offset error the major carry transition should occur for an analog value ? lsb below vin+ = vin?. offset error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value ? lsb above negative full scale. the last transition should occur at an analog value 1? lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temp er atu re d r i f t the temperature drift for zero error and gain error specifies the maximum change from the initial (25c) value to the value at t min or t max . power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. total harmonic distortion (thd) the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal, expressed as a percentage or in decibels relative to the peak carrier signal (dbc). signal-to-noise and distortion (sinad) ratio the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed db. effective number of bits (enob) using the following formula enob = ( sinad ? 1.76)/6.02 enob for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. signal-to-noise ratio (snr) the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in db. spurious-free dynamic range (sfdr) the difference in db between the rms amplitude of the input signal and the peak spurious signal. nyquist sampling when the frequency components of the analog input are below the nyquist frequency (f clock /2), this is often referred to as nyquist sampling. if sampling due to the effects of aliasing, an adc is not limited to nyquist sampling. higher sampled frequencies are aliased down into the first nyquist zone (dc ? f clock /2) on the output of the adc. the bandwidth of the sampled signal should not overlap nyquist zones and alias onto itself. nyquist sampling performance is limited by the bandwidth of the input sha and clock jitter (jitter adds more noise at higher input frequencies). two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product. out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. crosstalk coupling onto one channel being driven by a (?0.5 dbfs) signal when the adjacent interfering channel is driven by a full-scale signal. measurement includes all spurs resulting from both direct coupling and mixing components.
ad9248 rev. b | page 12 of 48 typical performance characteristics avdd, drvdd = 3.0 v, t = 25c, a in differential drive, full scale = 2 v, unless otherwise noted. ?120 10 magnitude (dbfs) 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 04446-060 snr = 72.6db sinad = 71.9db h2 = ?81.5dbc h3 = ?86.8dbc sfdr = 81.5db crosstalk second harmonic third harmonic figure 5. single-tone fft of channel a digitizing f in = 12.5 mhz while channel b is digitizing f in = 10 mhz ?120 10 magnitude (dbfs) 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 04446-061 snr = 70.5db sinad = 69.4db h2 = ?92.3dbc h3 = ?80.1dbc sfdr = 80.1dbc second harmonic third harmonic crosstalk figure 6. single-tone fft of channel a digitizing f in = 70 mhz while channel b is digitizing f in = 76 mhz ?120 10 magnitude (dbfs) 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) 04446-062 snr = 68.1db sinad = 68.0db h2 = ?83.4dbc h3 = ?83.1dbc sfdr = 75.1dbc second harmonic crosstalk figure 7. single-tone fft of channel a digitizing f in = 120 mhz while channel b is digitizing f in = 126 mhz adc sample rate (msps) 90 55 40 sfdr/snr (dbc) 85 80 75 70 65 60 45 50 55 60 65 95 100 50 04446-007 snr sfdr figure 8. ad9248-65 single-tone sfdr/snr vs. fs with f in = 32.5 mhz snr sfdr snr adc sample rate (msps) 90 55 40 sfdr/snr (dbc) 85 80 75 70 65 60 95 100 50 35 30 25 20 04446-008 figure 9. ad9248-40 single-tone sfdr/snr vs. fs with f in = 20 mhz sfdr snr adc sample rate (msps) 90 55 sfdr/snr (dbc) 85 80 75 70 65 60 95 100 50 0 5 10 15 20 04446-009 figure 10. ad9248-20 single-tone sfdr/snr vs. fs with f in = 10 mhz
ad9248 rev. b | page 13 of 48 snr sfdr snr input amplitude (dbfs) 90 sfdr/snr (dbc) 80 70 60 100 50 ?35 40 ?30 ?25 ?20 ?15 ?10 ?5 0 04446-010 figure 11. ad9248-65 single-tone sfdr/snr vs. a in with f in = 32.5 mhz snr sfdr snr input amplitude (dbfs) 90 sfdr/snr (dbc) 80 70 60 100 50 ?35 40 ?30 ?25 ?20 ?15 ?10 ?5 0 04446-011 figure 12. ad9248-40 single-tone sfdr/snr vs. a in with f in = 20 mhz snr sfdr snr input amplitude (dbfs) 90 sfdr/snr (dbc) 80 70 60 100 50 ?35 40 ?30 ?25 ?20 ?15 ?10 ?5 0 04446-012 figure 13. ad9248-20 single-tone sfdr/snr vs. a in with f in = 10 mhz snr sfdr snr input frequency (mhz) 90 sfdr/snr (dbc) 85 80 75 95 70 0 65 20 40 60 80 100 120 140 04446-013 figure 14. ad9248-65 single-tone sfdr/snr vs. f in snr sfdr snr 90 85 80 75 95 70 0 65 20 40 60 80 100 120 140 input frequency (mhz) sfdr/snr (dbc) 04446-014 figure 15. ad9248-40 single-tone sfdr/snr vs. f in snr sfdr snr 90 85 80 75 95 70 0 65 20 40 60 80 100 120 140 input frequency (mhz) sfdr/snr (dbc) 04446-015 figure 16. ad9248-20 single-tone sfdr/snr vs. f in
ad9248 rev. b | page 14 of 48 ?120 10 magnitude (dbfs) 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) imd = ?85dbc 04446-063 figure 17. dual-tone fft with f in 1 = 39 mhz and f in 2 = 40 mhz ?120 10 magnitude (dbfs) 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 frequency (mhz) imd = ?83dbc 04446-064 figure 18. dual-tone fft with f in 1 = 70 mhz and f in 2 = 71 mhz ?120 10 15 20 25 30 5 0 ?100 ?80 ?60 ?40 ?20 0 magnitude (dbfs) frequency (mhz) 04446-018 figure 19. dual-tone fft with f in 1 = 200 mhz and f in 2 = 201 mhz snr sfdr snr input amplitude (dbfs) 95 sfdr/snr (dbfs) 90 85 80 100 75 ?24 70 ?21 ?18 ?15 ?12 ?9 ?6 65 60 04446-019 figure 20. dual-tone sfdr/snr vs. a in with f in 1 = 45 mhz and f in 2 = 46 mhz snr sfdr snr input amplitude (dbfs) 95 sfdr/snr (dbfs) 90 85 80 100 75 ?24 70 ?21 ?18 ?15 ?12 ?9 ?6 65 60 04446-020 figure 21. dual-tone sfdr/snr vs. a in with f in 1 = 70 mhz and f in 2 = 71 mhz snr sfdr snr input amplitude (dbfs) 95 sfdr/snr (dbfs) 90 85 80 100 75 ?24 70 ?21 ?18 ?15 ?12 ?9 ?6 65 60 04446-021 figure 22. dual-tone sfdr/snr vs. a in with f in 1 = 200 mhz and f in 2 = 201 mhz
ad9248 rev. b | page 15 of 48 clock frequency (mhz) sinad (dbc) 72 70 74 0 68 20 40 60 sinad ?65 sinad ?40 sinad ?20 12.0 11.5 11.0 04446-022 enob figure 23. sinad vs. fs with nyquist input duty cycle (%) 85 sinad/sfdr (dbc) 80 75 70 95 65 30 60 40 45 50 55 60 65 55 50 dcs on (sfdr) dcs off (sinad) dcs off (sfdr) 90 35 dcs on (sinad) 04446-023 figure 24. sinad/sfdr vs. clock duty cycle temperature (c) 80 sinad/sfdr (db) 78 76 74 84 72 ?50 70 0 50 100 68 66 sinad sfdr 82 04446-024 figure 25. sinad/sfdr vs. temperature with f in = 32.5 mhz sample rate (msps) 500 avdd power (mw) 400 300 200 600 100 0 102030405060 ?65 ?40 ?20 04446-025 figure 26. analog power consumption vs. fs code inl (lsb) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 8000 6000 2000 4000 0 10000 12000 14000 16000 04446-026 figure 27. ad9248-65 typical inl code dnl (lsb) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 8000 6000 2000 4000 0 10000 12000 14000 16000 04446-027 figure 28. ad9248-65 typical dnl
ad9248 rev. b | page 16 of 48 equivalent circuits avdd v in+_a, vin?_a, v in+_b, vin?_b 04446-028 figure 29. equivalent analog input circuit drvdd 04446-029 figure 30. equivalent digital output circuit avdd clk_a, clk_b dcs, dfs, mux_select, shared_ref 04446-030 figure 31. equivalent digital input circuit
ad9248 rev. b | page 17 of 48 theory of operation the ad9248 consists of two high performance adcs that are based on the ad9235 converter core. the dual adc paths are independent, except for a shared internal band gap reference source, vref. each of the adc paths consists of a proprietary front end sha followed by a pipelined switched-capacitor adc. the pipelined adc is divided into three sections, consisting of a 4-bit first stage, followed by eight 1.5-bit stages, and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined through the digital correction logic block into a final 14-bit result. the pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the respective clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc and a residual multiplier to drive the next stage of the pipeline. the residual multiplier uses the flash adc output to control a switched-capacitor digital-to-analog converter (dac) of the same resolution. the dac output is subtracted from the stages input signal and the residual is amplified (multiplied) to drive the next pipeline stage. the residual multiplier stage is also called a multiplying dac (mdac). one bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sha that can be configured as ac- or dc-coupled in differential or single-ended modes. the output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. analog input the analog input to the ad9248 is a differential, switched- capacitor sha that has been designed for optimum perfor- mance while processing a differential input signal. the sha input accepts inputs over a wide common-mode range. an input common-mode voltage of midsupply is recommended to maintain optimal performance. the sha input is a differential switched-capacitor circuit. in figure 32 , the clock signal alternatively switches the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network creates a low-pass filter at the adc input; therefore, the precise values are dependent on the application. in if under-sampling applications, any shunt capacitors should be removed. in combination with the driving source impedance, they limit the input bandwidth. for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. these errors are reduced by the common-mode rejection of the adc. 5pf 5pf t t vin+ v in? c par t t h h c par 04446-031 figure 32. switched-capacitor input an internal differential reference buffer creates positive and negative reference voltages, reft and refb, respectively, that define the span of the adc core. the output common mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as: reft = ?( av d d + v ref ) refb = ?( av d d ? v ref ) span = 2 ( reft ? refb ) = 2 v ref the equations above show that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the v ref voltage. the internal voltage reference can be pin-strapped to fixed values of 0.5 v or 1.0 v or adjusted within the same range as discussed in the internal reference connection section. maximum snr performance is achieved with the ad9248 set to the largest input span of 2 v p-p. the relative snr degradation is 3 db when changing from 2 v p-p mode to 1 v p-p mode. the sha may be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. the minimum and maximum common-mode input levels are defined as: vcm min = v ref /2 vcm max = ( av d d + v ref )/2
ad9248 rev. b | page 18 of 48 the minimum common-mode input level allows the ad9248 to accommodate ground-referenced inputs. although optimum performance is achieved with a differential input, a single-ended source may be driven into vin+ or vin?. in this configuration, one input accepts the signal, while the opposite input should be set to midscale by connecting it to an appropriate reference. for example, a 2 v p-p signal may be applied to vin+, while a 1 v reference is applied to vin?. the ad9248 then accepts an input signal varying between 2 v and 0 v. in the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. however, the effect is less noticeable at lower input frequencies and in the lower speed grade models (ad9248-40 and ad9248-20). differential input configurations as previously detailed, optimum performance is achieved while driving the ad9248 in a differential input configuration. for baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set to avdd/2, and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. at input frequencies in the second nyquist zone and above, the performance of most amplifiers is not adequate to achieve the true performance of the ad9248. this is especially true in if under-sampling applications where frequencies in the 70 mhz to 200 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration, as shown in figure 33 . ad9248 vina vinb avdd agnd 2 v p-p 50 50 10pf 10pf 49.9 1k 1k 0.1 f 04446-032 figure 33. differential transformer coupling the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. single-ended input configuration a single-ended input may provide adequate performance in cost-sensitive applications. in this configuration, there is a degradation in sfdr and distortion performance due to the large input common-mode swing. however, if the source impedances on each input are matched, there should be little effect on snr performance. clock input and considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. the ad9248 provides separate clock inputs for each channel. the optimum performance is achieved with the clocks operated at the same frequency and phase. clocking the channels asynchronously may degrade performance significantly. in some applications, it is desirable to skew the clock timing of adjacent channels. the ad9248s separate clock inputs allow for clock timing skew (typically 1 ns) between the channels without significant performance degradation. the ad9248-65 contains two clock duty cycle stabilizers, one for each converter, that retime the nonsampling edge, providing an internal clock with a nominal 50% duty cycle. when proper track-and-hold times for the converter are required to maintain high performance, maintaining a 50% duty cycle clock is particularly important in high speed applications. it may be difficult to maintain a tightly controlled duty cycle on the input clock on the pcb (see figure 24 ). dcs can be enabled by tying the dcs pin high. the duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately 2 s to 3 s to allow the dll to acquire and settle to the new rate. high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency (f input ) due only to aperture jitter (t j ) can be calculated as () ? ? ? ? ? ? = 2 1 log20 in the equation, the rms aperture jitter, t j , represents the root- sum square of all jitter sources, which includes the clock input, analog input signal, and adc aperture jitter specification. under-sampling applications are particularly sensitive to jitter. for optimal performance, especially in cases where aperture jitter may affect the dynamic range of the ad9248, it is important to minimize input clock jitter. the clock input circuitry should use stable references; for example, use analog power and ground planes to generate the valid high and low digital levels for the ad9248 clock input. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
ad9248 rev. b | page 19 of 48 a single channel can be powered down for moderate power savings. the powered-down channel shuts down internal circuits, but both the reference buffers and shared reference remain powered on. because the buffer and voltage reference remain powered on, the wake-up time is reduced to several clock cycles. power dissipation and standby mode the power dissipated by the ad9248 is proportional to its sampling rates. the digital (drvdd) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. the digital drive current can be calculated by digital outputs i drvdd = v drvdd c load f clock n the ad9248 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause current glitches on the supplies that may affect converter performance. applications requiring the adc to drive large capacitive loads or large fanouts may require external buffers or latches. where n is the number of bits changing, and c load is the average load on the digital pins that changed. the analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates that increases with clock frequency. either channel of the ad9248 can be placed into standby mode independently by asserting the pdwn_a or pdwn_b pins. the data format can be selected for either offset binary or twos complement. see the data format section for more information. it is recommended that the input clock(s) and analog input(s) remain static during either independent or total standby, which results in a typical power consumption of 1 mw for the adc. note that if dcs is enabled, it is mandatory to disable the clock of an independently powered-down channel. otherwise, significant distortion results on the active channel. if the clock inputs remain active while in total standby mode, typical power dissipation of 12 mw results. timing the ad9248 provides latched data outputs with a pipeline delay of seven clock cycles. data outputs are available one propa- gation delay (t pd ) after the rising edge of the clock signal. refer to figure 2 for a detailed timing diagram. the internal duty cycle stabilizer can be enabled on the ad9248 using the dcs pin. this provides a stable 50% duty cycle to internal circuits. the minimum standby power is achieved when both channels are placed into full power-down mode (pdwn_a = pdwn_b = hi). under this condition, the internal references are powered down. when either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the reft and refb decoupling capacitors and to the duration of the power-down. typically, it takes approximately 5 ms to restore full operation with fully discharged 0.1 f and 10 f decoupling capacitors on reft and refb. the length of the output data lines and loads placed on them should be minimized to reduce transients within the ad9248. these transients can detract from the converters dynamic performance. the lowest typical conversion rate of the ad9248 is 1 msps. at clock rates below 1 msps, dynamic performance may degrade. b ?8 a ?7 b ?7 a ?6 b ?6 a ?5 b ?5 a ?4 b ?4 a ?3 b ?3 a ?2 b ?2 a ?1 b ?1 a 0 b 0 a 1 a ?1 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 b ?1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 analog input adc a analog input adc b clk_a = clk_b = mux_select d0_a to d11_a t pd t pd 04446-033 figure 34. multiplexed data format using the channel a output and the same clock tied to clk_a, clk_b, and mux_select
ad9248 rev. b | page 20 of 48 data format the ad9248 data output format can be configured for either twos complement or offset binary. this is controlled by the data format select pin (dfs). connecting dfs to agnd produces offset binary output data. conversely, connecting dfs to avdd formats the output data as twos complement. the output data from the dual adcs can be multiplexed onto a single 14-bit output bus. the multiplexing is accomplished by toggling the mux_select bit, which directs channel data to the same or opposite channel data port. when mux_select is logic high, the channel a data is directed to the channel a output bus, and the channel b data is directed to the channel b output bus. when mux_select is logic low, the channel data is reversed, that is, the channel a data is directed to the channel b output bus, and the channel b data is directed to the channel a output bus. by toggling the mux_select bit, multiplexed data is available on either of the output data ports. if the adcs run with synchronized timing, this same clock can be applied to the mux_select pin. any skew between clk_a, clk_b, and mux_select can degrade ac performance. it is recommended to keep the clock skew <100 ps. after the mux_select rising edge, either data port has the data for its respective channel; after the falling edge, the alternate channels data is placed on the bus. typically, the other unused bus would be disabled by setting the appropriate oeb high to reduce power consumption and noise. figure 34 shows an example of multiplex mode. when multiplexing data, the data rate is two times the sample rate. note that both channels must remain active in this mode and that each channels power- down pin must remain low. voltage reference a stable and accurate 0.5 v voltage reference is built into the ad9248. the input range can be adjusted by varying the reference voltage applied to the ad9248, using either the internal reference with different external resistor configurations or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. if the adc is being driven differentially through a transformer, the reference voltage can be used to bias the center tap (common-mode voltage). the shared reference mode allows the user to connect the references from the dual adcs together externally for superior gain and offset matching performance. if the adcs are to function independently, the reference decoupling can be treated independently and can provide superior isolation between the dual channels. to enable shared reference mode, the shared_ref pin must be tied high and the external differential references must be externally shorted. (reft_a must be externally shorted to reft_b, and refb_a must be shorted to refb_b.) internal reference connection a comparator within the ad9248 detects the potential at the sense pin and configures the reference into four possible states, which are summarized in table 7 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 35 ), setting vref to 1 v. connecting the sense pin to vref switches the reference amplifier output to the sense pin, completing the loop and providing a 0.5 v reference output. if a resistor divider is connected, as shown in figure 36 , the switch is again set to the sense pin. this puts the reference amplifier in a noninverting mode with the vref output defined as v ref = 0.5 (1 + r2 / r1 ) in all reference configurations, reft and refb drive the adc core and establish its input span. the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. vin+ vin? 10 f 10 f 0.1 f 0.1 f reft adc core select logic sense 0.1 f 0.5v ad9248 refb 0.1 f vref 04446-034 figure 35. internal reference configuration table 7. reference configuration summary selected mode sense voltage resulting v ref (v) resulting differential span (v p-p) external reference avdd n/ a 2 external reference internal fixed reference v ref 0.5 1.0 programmable reference 0.2 v to v ref 0.5 (1 + r2/r1) 2 v ref (see figure 36 ) internal fixed reference agnd to 0.2 v 1.0 2.0
ad9248 rev. b | page 21 of 48 external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or to improve thermal drift characteristics. when multiple adcs track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. a high precision external reference may also be selected to provide lower gain and offset temperature drift. figure 37 shows the typical drift characteristics of the internal reference in both 1 v and 0.5 v modes. when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7 k load. the internal buffer still generates the positive and negative full-scale references, reft and refb, for the adc core. the input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 v. if the internal reference of the ad9248 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 38 depicts how the internal reference voltage is affected by loading. vin+ vin? vref reft sense 0.5v ad9248 refb r1 r2 10 f 10 f 0.1 f 0.1 f 10 f adc core select logic 0.1 f 04446-035 figure 36. programmable reference configuration temperature (c) 0.2 vref error (%) 1.2 1.0 0.8 0.6 0.4 0 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 vref = 1v vref = 0.5v 04446-036 figure 37. typical vref drift load (ma) ?0.20 error (%) 0.05 0 ?0.05 ?0.10 ?0.15 ?0.25 0 0.5 1.0 1.5 2.0 2.5 3.0 0.5v error 1v error 04446-037 figure 38. vref accuracy vs. load
ad9248 rev. b | page 22 of 48 ad9248 lqfp evaluation board the evaluation board supports both the ad9238 and ad9248 and has five main sections: clock circuitry, inputs, reference circuitry, digital control logic, and outputs. a description of each section follows. tabl e 8 shows the jumper settings and notes assumptions in the comment column. four supply connections to tb1 are necessary for the evaluation board: the analog supply of the dut, the on-board analog circuitry supply, the digital driver dut supply, and the on- board digital circuitry supply. separate analog and digital supplies are recommended, and on each supply 3 v is nominal. each supply is decoupled on-board, and each ic, including the dut, is decoupled locally. all grounds should be tied together. clock circuitry the clock circuitry is designed for a low jitter sine wave source to be ac-coupled and level shifted before driving the 74vhc04 hex inverter chips (u8 and u9) whose output provides the clock to the part. the pot (r32 and r31) on the level shifting circuitry allows the user to vary the duty cycle if desired. the amplitude of the sine wave must be large enough for the trip points of the hex inverter and within the supplies to avoid noise from clipping. to ensure a 50% duty cycle internal to the part, the ad9248-65 has an on-chip duty cycle stabilizer circuit that is enabled by putting in jumper jp11. the duty cycle stabilizer circuitry should only be used at clock rates above 40 msps. each channel has its own clock circuitry, but normally both clock pins are driven by a single 74vhc04, and the solder jumper jp24 is used to tie the clock pins together. when the clock pins are tied together and only one 74vhc04 is being used, the series termination resistor for the other channel must be removed (either r54 or r55, depending on which inverter is being used). a data capture clock for each channel is created and sent to the output buffers in order to be used in the data capture system if needed. jumper jp25 and jumper jp26 are used to invert the data clock, if necessary, and can be used to debug data capture timing problems. analog inputs the ad9248 achieves the best performance with a differential input. the evaluation board has two input options for each channel, a transformer (xfmr) and an ad8138, both of which perform single-ended-to-differential conversions. the xfmr allows for the best high frequency performance, and the ad8138 is ideal for dc evaluation, low frequency inputs, and driving an adc differentially without loading the single-ended signal. the common-mode level for both input options is set to midsupply by a resistor divider off the avdd supply but can also be overdriven with an external supply using the (test points) tp12, tp13 for the ad8138s, and tp14, tp15 for the xfmrs. for low distortion of full-scale input signals when using an ad8138, put jumper jp17 and jumper jp22 in position b and put an external negative supply on the tp10 and tp11 testpoints. for best performance, use low jitter input sources and a high performance band-pass filter after the signal source, before the evaluation board (see figure 39 ). for xfmr inputs, use solder jumper jp13 and jumper jp14 for channel a, and jumper jp20 and jumper jp21 for channel b. for ad8138 inputs, use solder jumper jp15 and jumper jp16 for channel a, and jumper jp18 and jumper jp19 for channel b. remove all solder from the jumpers not being used. reference circuitry the evaluation board circuitry allows the user to select a reference mode through a series of jumpers and provides an external reference if necessary. please refer to table 9 to find the jumper settings for each reference mode. the external reference on the board is a simple resistor divider/zener diode circuit buffered by an ad822 (u4). the pot (r4) can be used to change the level of the external reference to fine adjust the adc full scale. digital control logic the digital control logic on the evaluation board is a series of jumpers and pull-down resistors used as digital inputs for the following pins on the ad9248: the power-down and output enable bar for each channel, the duty cycle restore circuitry, the twos complement output mode, the shared reference mode, and the mux_select pin. refer to table 8 for normal operating jumper positions. outputs the outputs of the ad9248 (and the data clock discussed earlier) are buffered by 74vhc541s (u2, u3, u7, u10) to ensure the correct load on the outputs of the dut, as well as the extra drive capability to the next part of the system. the 74vhc541s are latches, but on this evaluation board, they are wired and function as buffers. jumper jp30 can be used to tie the data clocks together if desired. if the data clocks are tied, the r39 or r40 resistor must be removed, depending on which clock circuitry is being used.
ad9248 rev. b | page 23 of 48 table 8. pcb jumpers jp description normal setting comment 1 reference out 1 v reference mode 2 reference in 1 v reference mode 3 reference out 1 v reference mode 4 reference out 1 v reference mode 5 reference out 1 v reference mode 6 shared reference out 7 shared reference out 8 pdwn b out 9 pdwn a out 10 shared reference out 11 duty cycle in duty cycle restore on 12 twos complement out 13 input in using xfmr input 14 input in using xfmr input 15 input out using xfmr input 16 input out using xfmr input 17 ad8138 supply a using xfmr input 18 input out using xfmr input 19 input out 20 input in 21 input in 22 ad8138 supply a 23 mux select out 24 tie clocks in using one signal for clock 25 data clock a 26 data clock out using one signal for clock 27 mux select in 28 oeb_a out 29 mux select out 30 data clock out 35 oeb_b out table 9. reference jumpers reference mode jp1 jp2 jp3 jp4 jp5 1 v internal o ut in out out out 0.5 v internal o ut out in out out external in out out out in ad9248 evaluation board sine source low jitter (hp8644) sine source low jitter (hp8644) band-pass filters output buffers input circuitry clock circuitry ad9248 04446-038 reference mode selection/external reference/control logic figure 39. pcb test setup
ad9248 rev. b | page 24 of 48 lqfp evaluation board bill of materials (bom) table 10. no. quantity reference designator device package value 1 18 c1, c2, c11, c12, c27, c28, c33, c34, c50, c51, c73 to c76, c87 to c90 capacitors acase 10 f 2 23 c3 to c10, c29 to c31, c56, c61 to c65, c77, c79, c80, c84 to c86 capacitors 0805 0.1 f 3 7 c13, c15, c18, c19, c21, c23, c25 capacitors 0603 0.001 f 4 15 c6, c14, c16, c17, c20, c22, c24, c26, c32, c35 to c40 capacitors 0603 0.1 f 5 4 c41 to c44 capacitors dcase 22 f 6 4 c45 to c48 capacitors 1206 0.1 f 7 2 c49, c53 capacitors acase 6.3 v 8 2 c52, c57 capacitors 0201 0.01 f 9 4 c54, c55, c68, c69 capacitors 0805 10 4 c58, c59 ,c70, c71 capacitors 0603 dnp 11 2 c60, c72 capacitors 0603 20 pf 12 1 d1 ad1580 sot-23can 1.2 v 13 1 j1 sam080upm 14 14 jp1 to jp5, jp8 to jp12, jp23, jp28, jp29, jp35 jprblk02 15 13 jp6, jp7, jp13, jp14 to jp16, jp18 to jp21, jp24, jp27, jp30 jprsld02 16 4 jp17, jp22, jp25, jp26 jprblk03 17 4 l1 to l4 ind1210 lc1210 10 h 18 6 r1, r2, r13, r14, r23, r27 resistors 1206 33 19 1 r3 resistor 1206 5.49 k 20 1 r4 resistor rv3299up 10 k 21 7 r5, r6, r38, r41, r43, r44, r51 resistors 0805 5 k 22 6 r7, r8, r19, r20, r52, r53 resistors 1206 49.9 23 8 r9, r18, r29, r30, r47 to r50 resistors 0805 1 k 24 6 r10, r12, r15, r24, r25, r28 resistors 1206 499 25 2 r11, r26 resistors 1206 523 26 4 r16, r17, r21, r22 resistors 1206 40 27 2 r31, r32 resistors rv3299w 10 k 28 4 r33 to r35, r42 resistors 0805 500 29 2 r36, r37 resistors 1206 10 k 30 2 r39, r40 resistors 0805 22 31 2 r54, r55 resistors 1206 0 32 16 rp1 to rp16 resistor pack rca74204 22 33 6 s1 to s6 sma200up 34 2 t1, t2 dip06rcup t1-1t 35 1 tb1 tblk06rem 36 4 tp1, tp3, tp5, tp7 looptp red 37 4 tp2, tp4, tp6, tp8 looptp blk 38 7 tp9, tp12 to tp17 loopmini wht 39 2 tp10, tp11 loopmini red 40 1 u1 64lqfp7x7 ad9248 41 4 u2, u3, u7, u10 sol20 74vhc541 42 1 u4 soic-8 ad822 43 2 u5, u6 so8nc7 ad8138 44 2 u8, u9 tssop-14 74vhc04
ad9248 rev. b | page 25 of 48 lqfp evaluation board schematics b tp8 blk tp2 blk avddin avdd red tp1 10 h l2 dutavddin tb1 dutavdd tp3 red 10 h l1 blk tp4 red tp5 10 hl4 dvddin agnd tb1 agnd drvddin tb1 tb1 tb1 dvdd dutdrvdd tp7 red blk tp6 10 h l3 r2 33 agnd;7 avdd;14 u8 12 u8 agnd;7 avdd;14 10 u8 8 jp26 3 2 wht tp16 74vhc04 74vhc04 74vhc04 b 13 11 9 jp25 2 1 3 r1 33 jp24 r54 0 tp17 wht clkao u9 agnd;7 avdd;14 12 agnd;7 avdd;14 u9 10 74vhc04 74vhc04 u9 agnd;7 avdd;14 9 74vhc04 u9 agnd;7 avdd;14 3 agnd;7 avdd;14 u9 6 agnd;7 avdd;14 u9 2 1 74vhc04 74vhc04 74vhc04 r53 49.9 s6 r32 10k r42 500 c84 0.1 f clka cw cw r31 10k avdd r34 500 r35 500 c77 0.1 f r52 49.9 c73 10 f 6.3v s5 c79 0.1 f clkb avdd c74 10 f 6.3v c80 0.1 f u8 agnd;7 avdd;14 5 agnd;7 avdd;14 u8 4 3 u8 agnd;7 avdd;14 74vhc04 74vhc04 74vhc04 agnd;7 avdd;14 1 dataclkb 13 11 avdd r33 500 dutclka 5 dataclka dutclkb c42 22 f 25v c46 0.1 f c41 22 f 25v c45 0.1 f c44 22 f 25v c48 0.1 f c43 22 f f25v c47 0.1 f r55 0 8 4 a a 1 2 1 2 3 tb1 5 4 6 6 04446-039 figure 40. evaluation board schematic
ad9248 rev. b | page 26 of 48 r20 49.9 r8 49.9 r19 49.9 r7 49.9 c59 dnp c58 dnp c71 dnp c70 dnp 0.1 f c65 c64 0.1 f r18 1k r50 1k r29 1k r9 1k r30 1k r47 1k c85 0.1 f c63 0.1 f c68 val c69 val val c55 val c54 c56 0.1 f c62 0.1 f c61 0.1 f c 5 3 1 0 v 6 . 3 v c49 10v 6.3v r21 40 r22 40 r23 33 jp18 jp19 r24 499 r25 499 jp22 2 s4 jp20 jp21 t1 t1?1t 6 4 1 2 3 jp14 jp13 s2 r14 33 vin+_a vin?_a vin+_b vin?_b jp17 2 3 1 499 r12 jp16 jp15 r13 33 r17 40 r27 33 t1?1t t2 3 2 1 4 6 s3 tp11 red r16 40 c87 10 f 6.3v tp12 wht tp13 wht tp14 wht tp15 wht u6 1 8 6 3 2 4 5 u5 5 4 2 3 6 8 1 c88 10 f 6.3v c50 10 f 6.3v c51 10 f 6.3v r49 1k r48 1k r15 499 c86 0.1 f r10 499 s1 r11 523 r26 523 r28 499 c60 20pf c72 20pf nc = 5 nc = 5 ad8138 ad8138 xfmr input b xfmr input a s p s p sheet 3 sheet 3 a ?in +in vee vcc voc vo+ vo? avdd avdd avdd avdd avdd amp input a amp input b ?in +in vee vcc voc vo+ vo? b b a tp10 red c89 10 f 6.3v c90 10 f 6.3v 13 o o o o 04446-040 avdd figure 41. evaluation board schematic (continued)
ad9248 rev. b | page 27 of 48 dutavdd avdd avdd r36 10k jp6 r41 5k r51 5k avdd c1 10 f 6.3v avdd r44 5k c34 10 f 6.3v vin+_b vin?_b vin?_a otra da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 otrb db13 db12 db11 db10 db9 db7 db6 db5 db4 db3 db2 db1 d1 2 1 dutavdd dutdrvdd r4 10k db0 db8 da0 agnd;4 avdd;8 u4 2 1 3 agnd;4 avdd;8 u4 out 5 7 6 vin+_a c35 0.1 f c37 0.1 f c38 0.1 f c36 0.1 f r3 5.49k r5 5k c30 0.1 f c29 0.1 f 0.1 f r43 5k r6 5k r38 5k u1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 32 31 30 29 28 27 26 25 48 24 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 c12 10 f 6.3v tp9 wht jp7 avdd clkao dutclkb dutclka r37 10k c52 0.01 f 1.2v ad822 ad822 ad9248 vin+_a vin?_a avss2 avdd2 reft_a refb_a vref sense refb_b reft_b avdd3 avss3 vin?_b vin+_b avss4 avdd4 clk_b dutyen dfs pdwn_b d0_b (lsb) d5_a d4_a d3_a d2_a d1_a d0_a (lsb) drvdd2 drvss2 otr_b (msb) d13_b d12_b d11_b d10_b d9_b d8_b avss1 d1_b d6_a d2_b d3_b d4_b drvss1 drvdd1 d5_b d6_b d7_b d7_a d8_a d9_a drvdd3 drvss3 d10_a d11_a d12_a (msb) d13_a otr_a pdwn_a mux_select shared_ref clk_a avdd1 oeb_a oeb_b c31 jp11 jp12 jp2 jp3 jp4 jp1 c57 0.01 f jp5 c32 0.1 f c39 0.1 f c40 0.1 f c33 10 f 6.3v cw jp35 jp8 c24 0.1 f c25 0.001 f c26 0.1 f c13 0.001 f c14 0.1 f c11 10 f 6.3v c23 0.001 f jp23 jp27 jp29 jp28 jp10 c22 0.1 f c15 0.001 f c17 0.1 f c18 0.001 f c19 0.001 f c20 0.1 f c21 0.001 f c16 0.1 f jp9 c2 10 f 6.3v avdd +in ?in out +in ?in 04446-041 figure 42. evaluation board schematic (continued)
ad9248 rev. b | page 28 of 48 4 2 2 rp11 dvdd u10 18 2 11 12 13 14 15 16 17 20 10 19 1 9 8 7 6 5 4 3 u7 3 4 5 6 7 8 9 1 19 10 20 17 16 15 14 13 12 11 2 da13 da12 da11 da10 da9 da8 da7 da6 da5 da4 da3 da2 da1 rp10 4 rp10 6 3 rp4 6 3 rp42 rp3 4 rp3 6 3 rp3 2 rp3 8 1 rp2 4 rp2 6 3 rp22 rp2 8 1 rp14 rp1 6 3 rp1 2 c3 0.1 f c10 0.1 f c9 0.1 f c8 0.1 f rp4 8 1 rp4 4 otra da0 rp102 rp10 8 1 rp94 rp9 6 5 7 5 3 rp9 2 rp9 8 7 5 7 5 7 1 rp12 4 rp12 6 3 rp12 rp12 8 1 rp11 rp11 6 3 rp11 c28 10 f 6.3v 8 1 c75 10 f 6.3v jp30 r39 22 r40 22 dataclka dataclkb rp1 22 8 1 a2 a3 a4 a5 a6 a7 a8 g1 g2 gnd vcc y2 y3 y4 y5 y6 y7 y8 a1 y1 74vhc541 a2 a3 a4 a5 a6 a7 a8 g1 g2 gnd vcc y2 y3 y4 y5 y6 y7 y8 a1 y1 74vhc541 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 sam080upm 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 a8 y8 22 sam080upm 18 2 2 3 1 4 3 4 4 4 2 2 22 2 4 2 4 2 4 2 1 19 1 9 11 dvdd c7 0.1 f c6 0.1 f c5 0.1 f c4 0.1 f c27 10 f 6.3v c76 10 f 6.3v 18 2 11 12 13 14 15 16 17 10 20 9 8 7 6 5 4 3 u3 3 4 5 6 7 8 1 19 10 20 17 16 15 14 13 12 2 da13 da12 da11 da10 da9 da8 da6 da5 da4 da3 da2 da1 da0 rp14 rp14 6 3 rp8 6 3 5 4 rp8 rp7 rp7 6 3 rp7 rp7 8 1 rp6 rp6 6 3 rp6 rp6 8 1 rp5 rp5 6 3 rp5 rp8 8 1 otrb rp14 rp14 8 1 rp13 rp13 6 5 7 5 7 3 rp13 rp13 8 1 rp16 rp16 rp16 7 8 6 5 rp16 rp15 5 6 rp15 rp15 7 a2 a3 a4 a5 a6 a7 g1 g2 gnd vcc y2 y3 y4 y5 y6 y7 a1 y1 74vhc541 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 rp5 22 22 22 22 22 22 22 22 22 22 22 22 22 22 18 rp8 22 1 da7 rp15 8 22 13 11 9 7 5 3 1 39 37 35 33 31 29 27 25 23 21 19 17 15 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 53 51 49 47 45 43 41 79 77 75 73 71 69 67 65 63 61 59 57 55 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 5 7 7 5 7 5 7 5 j1 header up male no shroud u2 a2 a3 a4 a5 a6 a7 a8 g2 g1 gnd vcc y2 y3 y4 y5 y6 y7 y8 a1 y1 74vhc541 j1 header up male no shroud 8 7 5 7 5 7 5 7 04446-042 figure 43. evaluation board schematic (continued)
ad9248 rev. b | page 29 of 48 lqfp pcb layers 04446-043 figure 44. pcb top layer
ad9248 rev. b | page 30 of 48 04446-044 figure 45. bottom layer
ad9248 rev. b | page 31 of 48 04446-045 figure 46. pcb ground plane
ad9248 rev. b | page 32 of 48 0 4446-046 figure 47. pcb split power plane
ad9248 rev. b | page 33 of 48 0 4446-049 figure 48. pcb top silkscreen (note that the pcb supports both the ad9238 and ad9248 lqfp)
ad9248 rev. b | page 34 of 48 0 4446-048 figure 49. pcb bottom silkscreen
ad9248 rev. b | page 35 of 48 dual adc lfcsp pcb the pcb requires a low jitter clock source, analog sources, and power supplies. the pcb interfaces directly with analog devices standard dual-channel data capture board (hsc-adc-eval-dc), which together with adis adc analyzer? software allows for quick adc evaluation. power connector power is supplied to the board via three detachable 4-lead power strips. table 11. power connector terminal comments vcc 1 3.0 v analog supply for adc vdd 1 3.0 v output supply for adc vdl 1 3.0 v supply circuitry vref optional external vref +5 v optional op amp supply ?5 v optional op amp supply 1 vcc, vdd, and vdl are the minimu m required power connections. analog inputs the evaluation board accepts a 2 v p-p analog input signal centered at ground at two smb connectors, input a and input b. these signals are terminated at their respective transformer primary side. t1 and t2 are wideband rf transformers that provide the single-ended-to-differential conversion, allowing the adc to be driven differentially, minimizing even-order harmonics. the analog signals can be low-pass filtered at the transformer secondary to reduce high frequency aliasing. optional operational amplifier the pcb has been designed to accommodate an optional ad8139 op amp that can serve as a convenient solution for dc-coupled applications. to use the ad8139 op amp, remove c14, r4, r5, c13, r37, and r36. place r22, r23, r30, and r24. clock the clock inputs are buffered on the board at u5 and u6. these gates provide buffered clocks to the on-board latches, u2 and u4, adc input clocks, and dra, drb that are available at the output connector p3, p8. the clocks can be inverted at the timing jumpers labeled with the respective clocks. the clock paths also provide for various termination options. the adc input clocks can be set to bypass the buffers at solder bridges p2, p9 and p10, p12. an optional clock buffer u3, u7 can also be placed. the clock inputs can be bridged at tiea, tieb (r20, r40) to allow one to clock both channels from one clock source; however, optimal performance is obtained by driving j2 and j3. table 12. jumpers terminal comments oeb a output enable for a side pdwn a power-down a mux mux input shared ref shared reference input dr a invert dr a lata invert a latch clock enc a invert encode a oeb b output enable for b side pdwn b power-down b dfs data format select shared ref shared reference input dr b invert dr b latb invert b latch clock enc b invert encode b voltage reference the adc sense pin is brought out to e41, and the internal reference mode is selected by placing a jumper from e41 to ground (e27). external reference mode is selected by placing a jumper from e41 to e25 and e30 to e2. r56 and r45 allow for programmable reference mode selection. data outputs the adc outputs are latched on the pcb at u2, u4. the adc outputs have the recommended series resistors in line to limit switching transient effects on adc performance.
ad9248 rev. b | page 36 of 48 lfcsp evaluation board bill of materials (bom) table 13. no. quantity reference designator device package value 1 2 c1, c3 capacitors 0201 20 pf 2 7 c2, c5, c7, c9, c10, c22, c36 capacitors 0805 10 f 3 44 c4, c6, c8, c11 to c15, c20, c21, c24 to c27, c29 to c35, c39 to c61 capacitors 0402 0.1 f 4 6 c16 to c19, c37, c38 capacitors tajd 10 f 5 2 c23, c28 capacitors 0201 0.1 f 6 6 j1 to j6 smbs 7 3 p1, p4, p11 power connector posts z5.531.3425.0 wieland 8 3 p1, p4, p11 detachable connectors 25.602.5453.0 wieland 9 2 p3 1 , p8 connectors 10 4 r1, r2, r32, r34 resistors 0402 36 11 6 r3, r6, r7, r8, r11, r14, r33, r42, r51, r61 resistors 0402 50 12 4 r4, r5, r36, r37 resistors 0402 33 13 9 r9, r10, r12, r13, r20, r35, r38, r40, r43 resistors 0402 0 14 6 r15, r16, r18, r26, r29, r31 resistors 0402 499 15 2 r17, r25 resistors 0402 525 16 27 r19, r21, r27, r28, r39, r41, r44, r46 to r49, r52, r54, r55, r57 to r60, r62 to r70 resistors 0402 1 k 17 4 r22 to r24, r30 resistors 0402 40 18 2 r45, r56 resistors 0402 10 k 19 1 r50 resistor 0402 22 20 8 rz1 to rz6, rz9, rz10 resistor pack 220 21 2 t1, t2 transformers awt-1wt mini-circuits? 22 1 u1 ad9248 lfcsp-64 23 2 u2, u425 sn74lvth162374 tssop-48 24 2 u3 2 , u7 sn74lvc1g04 sot-70 25 2 u5, u6 sn74vcx86 so-14 26 2 u11, u12 ad8139 so-8/ep 27 4 r6, r8, r33, r42 resistors 0402 100 1 p3, p8 implemented as one 80-pin connector samtec tsw-140-08-l-d-ra. 2 u3, u7 not placed.
ad9248 rev. b | page 37 of 48 lfcsp pcb schematics d7_a d7a 49 d8_a d8a 50 d9_a d9a 51 drvdd2 52 drgnd2 53 d10_a d10a 54 d11_a d11a 55 d12_a d12a 56 d13_a d13a 57 otr_a otra 58 oeb_a 59 pdwn_a 60 mux_sel 61 sh_ref 62 clk_a 63 avdd5 vd 64 epad 65 d7b d7_b 32 d6b 31 d5_b 30 drvdd 29 drgnd 28 d4b d4_b 27 d3b d3_b 26 d2b d2_b 25 d1b 24 23 22 21 20 dcs 19 encb d6_b d1_b d0_b oeb_b pdwn_b dfs clk_b d6_a d6a 48 d5_a d5a 47 d4_a d4a 46 d3_a d3a 45 d2_a d2a 44 d1_a d1a 43 d0_a d0a 42 drvdd1 41 drgnd1 40 otr_b otrb 39 d13_b d13b 38 d12_b d12b 37 d11_b d11b 36 d10_b d10b 35 d9_b d9b 34 d8_b d8b 33 1 agnd 2 vin_a 3 vin_ab 4 agnd1 vd 5 avdd1 6 reft_a 7 refb_a vref 8 vref sense 9 sense 10 refb_b 11 reft_b vd 12 avdd2 13 agnd2 14 vin_bb 15 vin_b 16 agnd3 vcc 14 4b 13 4a 12 4y 11 3b 10 3a 9 3y 8 1a 1b 1y 2a 2b 2y gnd 1 2 3 4 5 6 7 gnd 7 2y 6 2b 5 2a 4 1y 3 1b 2 1a 1 3y 3a 3b 4y 4a 4b vcc 8 9 10 11 12 13 14 18 vd avdd3 17 d0b d5b + + + + + + enca vref c30 0.1 f r45 10k r56 10k e2 e27 e25 e30 e41 vd c11 0.1 f sense ext_vref c2 10 f vref and sense circuit mux r35 0 r38 0 r20 0 r40 0 r14 50 j5 tieb tiea to tie clocks together c4 0.1 f vdd vdd c6 0.1 f e22 e24 vd r67 1k r68 1k r70 1k r69 1k e21 e40 vd e26 e29 vd e31 e33 vd pads to short references together p15 p16 p18 p17 refta reftb refba refbb refb_b reft_b ampoutb r36 33 r37 33 ampoutbb c3 20pf c28 0.1 f c7 10 f c54 0.1 f c23 0.1 f c5 10 f c55 0.1 f c24 0.1 f c26 0.1 f c29 0.1 f c27 0.1 f h3 mthole6 h1 mthole6 h2 mthole6 h4 mthole6 4 12 3 4 12 3 4 12 3 p5 p6 p7 vd vdd vdl c37 10 f c38 10 f c16 10 f c17 10f c18 10f c19 10 f c39 0.1 f c43 0 . 1 f c44 0 . 1 f c45 0 . 1 f +5v ?5v ext_vref vdl vdd vd p11 p4 p1 e34 e16 vd vd r55 1k e37 e38 r48 1k 0 r12 0 r13 e35 e36 vd r49 1k c41 0.1 f vd vd j2 encode b r51 50 c42 0.1 f r54 1k r52 1k p2 p9 u3 p13 encb vd vd c22 10 f c57 0.1 f r6 100 r8 100 tieb 1 2 3 5 4 sn74lvc1g04 nc a gnd vcc y 1 2 3 5 4 sn74lvc1g04 nc a gnd vcc y p10 p12 c36 10f c58 0.1 f enca vd vd r33 100 r42 100 r50 22 r43 0 u1 e13 e12 vd vd r47 1k e15 e14 r46 1k 0 r9 0 r10 clklatb drb dra clklata j6 r61 50 c56 0.1 f vd j3 encode a r11 50 c40 0.1 f r41 1k tiea r39 1k vd c25 0.1 f e3 e4 vd r44 1k p14 e6 e5 vd e20 e18 vd e9 e7 vd r66 1k r65 1k r64 1k e10 e17 r63 1k r62 1k vd vdd c8 0.1 f mux dut clock selectable to be direct or buffered 74lcx86 74lcx86 r4 33 j1 ain b c13 0.1 f r59 1k r7 50 ampinb c10 10 f c12 0.1 f e43 e42 c9 10 f c31 0.1 f r57 1k 1 2 3 6 5 4 ctapb r5 33 1 2 3 6 5 4 ctapa ampoutab ampouta c14 0.1 f ampina r3 50 j4 c1 20pf vd ?5v +5v vd vdd vdl ext_vref ctapa r58 1k vd vd r60 1k ctapb t1 t2 see below dut clock selectable to be direct or buffered u5 u6 u7 ain a 04446-050 figure 50. pcb schematic (1 of 3)
ad9248 rev. b | page 38 of 48 r8 r7 r6 r5 r4 r3 r1 r2 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 220 220 220 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 header40 220 sn74lvch16373a u2 1d1 1d2 1d3 1d4 1d5 1d6 1d7 1d8 1q1 1q2 1q3 1q4 1q5 1q6 1q7 1q8 2d1 2d2 2d3 2d4 2d5 2d6 2d7 2d8 2q1 2q2 2q3 2q4 2q5 2q6 2q7 2q8 gnd le1 le2 vcc oe1 oe2 vcc vcc vcc gnd gnd gnd gnd gnd gnd gnd 220 r8 r7 r6 r5 r4 r3 r1 r2 220 220 220 sn74lvch16373a u4 1d1 1d2 1d3 1d4 1d5 1d6 1d7 1d8 1q1 1q2 1q3 1q4 1q5 1q6 1q7 1q8 2d1 2d2 2d3 2d4 2d5 2d6 2d7 2d8 2q1 2q2 2q3 2q4 2q5 2q6 2q7 2q8 gnd le1 le2 vcc oe1 oe2 vcc vcc vcc gnd gnd gnd gnd gnd gnd gnd q = output d = input 47 46 44 43 41 40 38 37 2 3 5 6 8 9 11 12 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 4 10 15 21 45 39 34 28 48 25 7 18 42 31 1 24 clklatb clklatb clklata vdl vdl vdl rz6 rso16iso rz5 rso16iso 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz4 rso16iso 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz3 rso16iso 47 46 44 43 41 40 38 37 2 3 5 6 8 9 11 12 36 35 33 32 30 29 27 26 13 14 16 17 19 20 22 23 4 10 15 21 45 39 34 28 48 25 7 18 42 31 1 24 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz1 rso16iso 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 p3 rz9 rso16iso rz10 rso16iso d9q d8q d7q d6q d5q d4q d3q d2q d1q d9p d8p d7p d6p d5p d4p d3p d2p d1p d8a d9a d2a d3a d4a d5a d6a d7a d0a d1a gnd d9p d8p d7p d6p d5p d4p d3p d2p d1p d0p gnd dra drb otra d13a d12a d11a d10a d7b d9b d8b otrb d13b d12b d11b d10b dorp d13p d12p d11p d10p dorq d13q d12q d11q d10q d9q d0q d8q d1q d2q d6q d7q d3q d4q d5q d13p d12p d11p d10p d0p dorp d13q d12q d11q d10q d0q dorq vdl vdl vdl vdl clklata 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz2 rso16iso d5b d6b d4b d3b d2b d1b d0b r8 r7 r6 r5 r4 r3 r1 r2 r8 r7 r6 r5 r4 r3 r1 r2 r8 r7 r6 r5 r4 r3 r1 r2 q = output d = input r8 r7 r6 r5 r4 r3 r1 r2 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 r8 r7 r6 r5 r4 r3 r1 r2 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 r8 r7 r6 r5 r4 r3 r1 r2 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 header40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 p8 vdl c49 0.1 f c48 0.1 f c47 0.1 f c46 0.1 f c53 0.1 f c52 0.1 f c51 0.1 f c50 0.1 f 39 39 vdl 04446-051 figure 51. pcb schematic (2 of 3)
ad9248 rev. b | page 39 of 48 +in +out ?in ?out epad nc v+ v? vocm ad8139 c20 0.1 f 8 4 1 5 9 7 3 6 2 u12 c35 0.1 f r29 499 r30 40 r25 525 ampoutb ampoutbb +5v ?5v ampinb c34 0.1 f r28 1k r27 1k vd r24 40 +in +out ?in ?out epad nc v+ v? vocm ad8139 c21 0.1 f 8 4 1 5 9 7 3 6 2 u11 c32 0.1 f r17 525 r22 40 r16 499 ampoutab ampouta +5v ?5v ampina c33 0.1 f r19 1k r21 1k vd r23 40 op amp input off pin 1 of transformer 04446-052 r31 499 c61 r26 499 c15 r15 499 c60 r18 499 c59 figure 52. pcb schematic (3 of 3)
ad9248 rev. b | page 40 of 48 lfcsp pcb layers 04446-053 figure 53. pcb top-side silkscreen
ad9248 rev. b | page 41 of 48 04446-054 figure 54. pcb top-side copper routing
ad9248 rev. b | page 42 of 48 04446-055 figure 55. pcb ground layer
ad9248 rev. b | page 43 of 48 04446-056 figure 56. pcb split power plane
ad9248 rev. b | page 44 of 48 04446-057 figure 57. pcb bottom-side copper routing
ad9248 rev. b | page 45 of 48 04446-058 figure 58. pcb bottom-side silkscreen thermal considerations the ad9248 lfcsp has an integrated heat slug that improves the thermal and electrical properties of the package when locally attached to a ground plane at the pcb. a thermal (filled) via array to a ground plane beneath the part provides a path for heat to escape the package, lowering junction temperature. improved electrical performance also results from the reduction in package parasitics due to proximity of the ground plane. recommended array is 0.3 mm vias on 1.2 mm pitch. ja = 26.4c/w with this recommended configuration. soldering the slug to the pcb is a requirement for this package. 04446-059 figure 59. thermal via array
ad9248 rev. b | page 46 of 48 outline dimensions compliant to jedec standards ms-026-bbd 051706-a top view (pins down) 1 16 17 33 32 48 49 64 0.23 0.18 0.13 0.40 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 figure 60. 64-lead low profile quad flat package [lqfp] (st-64-1) dimensions shown in millimeters pin 1 indicator top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max * 4.85 4.70 sq 4.55 exposed pad (bottom view) * compliant to jedec standards mo-220-vmmd-4 except for exposed pad dimension 082908-b seating plane pin 1 indicator 0.30 0.25 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 61. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-1) dimensions shown in millimeters
ad9248 rev. b | page 47 of 48 ordering guide model 1 temperature range package description package option ad9248bstz-20 C40c to +85c 64-lead low profile quad flat package (lqfp) st-64-1 ad9248bstz-40 C40c to +85c 64-lead low profile quad flat package (lqfp) st-64-1 ad9248bstz-65 C40c to +85c 64-lead low profile quad flat package (lqfp) st-64-1 ad9248bstzrl-20 C40c to +85c 64-lead low pr ofile quad flat package (lqfp) st-64-1 ad9248bstzrl-40 C40c to +85c 64-lead low pr ofile quad flat package (lqfp) st-64-1 ad9248bstzrl-65 C40c to +85c 64-lead low pr ofile quad flat package (lqfp) st-64-1 ad9248bcpz-20 C40c to +85c 64-lead lead fr ame chip scale package (lfcsp_vq) cp-64-1 ad9248bcpz-40 C40c to +85c 64-lead lead fr ame chip scale package (lfcsp_vq) cp-64-1 ad9248bcpz-65 C40c to +85c 64-lead lead fr ame chip scale package (lfcsp_vq) cp-64-1 AD9248BCPZRL-20 C40c to +85c 64-lead lead fr ame chip scale package (lfcsp_vq) cp-64-1 ad9248bcpzrl-40 C40c to +85c 64-lead lead fr ame chip scale package (lfcsp_vq) cp-64-1 ad9248bcpzrl-65 C40c to +85c 64-lead lead fr ame chip scale package (lfcsp_vq) cp-64-1 ad9248bst-65ebz evaluation board with ad9248bstz-65 ad9248bcp-65ebz evaluation board with ad9248bcpz-65 1 z = rohs compliant part.
ad9248 rev. b | page 48 of 48 notes ?2005C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04446C0C11/10(b)

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